[MA/BA/DA] Multicore Chip Programming (for mobile devices)

[stulova]

The SSS/ICE chair of ET offers several projects in the scope of embedded software for multicore chips.

Background
Heterogeneous multiprocessor chip architectures can provide high scalability and power efficiency. However, popularization of such architectures introduced a huge software productivity gap.
While hardware designers know how to scale number of cores integrated on the same chip the problem of how to effectively program such platforms still remains unclear.
One of the open issue is which programming model to select. C programming language was used for many decades and it's very familiar to embedded software developers.
However, C only allows to specify sequential computation and therefore doesn't match novel hardware architectures.
We are focusing on signal processing and multimedia applications that contain native algorithmic concurrency in form of isolated computation kernels communicating with each other via unidirectional first-in-first-out links.
This model can be efficiently used as a parallel specification to be mapped on the available processing cores.
Other, important design problems we are tackling are: parallelism extraction from C code, mapping to multicore architectures, automatic software synthesis.

We offer the following topics:
- Efficient compilation and automatic optimization of stream programs for novel heterogeneous multicore platforms
- Mapping and scheduling of programs to available on the target platform processing and interconnect resources
- Automatic SW synthesis to target platforms (e.g. TI OMAP, Synopys VP, etc)
- Debugging support for multicore SW development
- and many others...

Requirements:
Good C/C++ programmming skills

Contact:
Please, refer to these pages for more details:
http://www.ice.rwth-aachen.de/institute ... va/theses/
http://www.ice.rwth-aachen.de/institute ... tudio-sss/
Or contact directly to Anastasia Stulova by email: stulova(at)ice.rwth-aachen.de